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μ PD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
Test Access Port (TAP) Pins
Pin name
Pin assignments
Description
TCK
2R
Test Clock Input.
All input are captured on the rising edge of TCK and all outputs
propagate from the falling edge of TCK.
TMS
TDI
TDO
10R
11R
1R
Test Mode Select. This is the command input for the TAP controller state machine.
Test Data Input. This is the input side of the serial registers placed between TDI and
TDO. The register placed between TDI and TDO is determined by the state of the TAP
controller state machine and the instruction that is currently loaded in the TAP instruction.
Test Data Output. This is the output side of the serial registers placed between TDI and
TDO. Output changes in response to the falling edge of TCK.
Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held HIGH
for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.
JTAG DC Characteristics (T A = 0 to 70°C, V DD = 1.8 ± 0.1 V, unless otherwise noted)
Parameter
JTAG Input leakage current
JTAG I/O leakage current
Symbol
I LI
I LO
Conditions
0 V ≤ V IN ≤ V DD
0 V ≤ V IN ≤ V DD Q,
MIN.
? 5.0
? 5.0
MAX.
+5.0
+5.0
Unit
μ A
μ A
Outputs disabled
JTAG input HIGH voltage
JTAG input LOW voltage
V IH
V IL
1.3
? 0.3
V DD +0.3
+0.5
V
V
JTAG output HIGH voltage
JTAG output LOW voltage
V OH1
V OH2
V OL1
V OL2
| I OHC | = 100 μ A
| I OHT | = 2 mA
I OLC = 100 μ A
I OLT = 2 mA
1.6
1.4
0.2
0.4
V
V
V
V
Data Sheet M19962EJ2V0DS
23
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